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Espressif Systems /ESP32-S3 /SPI1 /CTRL

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Interpret as CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (FDUMMY_OUT)FDUMMY_OUT 0 (FDOUT_OCT)FDOUT_OCT 0 (FDIN_OCT)FDIN_OCT 0 (FADDR_OCT)FADDR_OCT 0 (FCMD_DUAL)FCMD_DUAL 0 (FCMD_QUAD)FCMD_QUAD 0 (FCMD_OCT)FCMD_OCT 0 (FCS_CRC_EN)FCS_CRC_EN 0 (TX_CRC_EN)TX_CRC_EN 0 (FASTRD_MODE)FASTRD_MODE 0 (FREAD_DUAL)FREAD_DUAL 0 (RESANDRES)RESANDRES 0 (Q_POL)Q_POL 0 (D_POL)D_POL 0 (FREAD_QUAD)FREAD_QUAD 0 (WP)WP 0 (WRSR_2B)WRSR_2B 0 (FREAD_DIO)FREAD_DIO 0 (FREAD_QIO)FREAD_QIO

Description

SPI1 control register

Fields

FDUMMY_OUT

In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller.
FDOUT_OCT

Set this bit to enable 8-bit-mode(8-bm) in DOUT phase.
FDIN_OCT

Set this bit to enable 8-bit-mode(8-bm) in DIN phase.
FADDR_OCT

Set this bit to enable 8-bit-mode(8-bm) in ADDR phase.
FCMD_DUAL

Set this bit to enable 2-bit-mode(2-bm) in CMD phase.
FCMD_QUAD

Set this bit to enable 4-bit-mode(4-bm) in CMD phase.
FCMD_OCT

Set this bit to enable 8-bit-mode(8-bm) in CMD phase.
FCS_CRC_EN

For SPI1, initialize crc32 module before writing encrypted data to flash. Active low.
TX_CRC_EN

For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable
FASTRD_MODE

This bit should be set when SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD or SPI_MEM_FREAD_DUAL is set.
FREAD_DUAL

In hardware 0x3B read operation, DIN phase apply 2 signals. 1: enable 0: disable.
RESANDRES

The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.
Q_POL

The bit is used to set MISO line polarity, 1: high 0, low
D_POL

The bit is used to set MOSI line polarity, 1: high 0, low
FREAD_QUAD

In hardware 0x6B read operation, DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable.
WP

Write protect signal output when SPI is idle. 1: output high, 0: output low.
WRSR_2B

Two bytes data will be written to status register when it is set. 1: enable 0: disable.
FREAD_DIO

In hardware 0xBB read operation, ADDR phase and DIN phase apply 2 signals(2-bit-mode). 1: enable 0: disable.
FREAD_QIO

In hardware 0xEB read operation, ADDR phase and DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data